Design of Digital Filters for Multi-standard Transceivers

This paper addresses on three different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area, delay and dynamic power consumption. The proposed decimation filter architectures reflect the considerable reduction in area and dynamic power consumption without degradation of performance. The filter coefficients are derived from MATLAB, the filter architectures are implemented and tested using Xilinx SPARTAN FPGA .First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the two different encoding schemesi.e. Canonic Signed Digit (CSD) and Minimum Signed Digit (MSD) are used for filter coefficients and then the architecture performances are tested .The results of CSD and MSD based architectures show a considerable reduction in the area and power against the conventional number system based filter design implementation. The implementation results reflect that considerable reduction in area of 47.89% and dynamic power reduction of 28.64% are achieved using hybrid architecture.